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CXL 3.1 Specification Now AvailableLearn more about the fabric improvements and extensions, TSP, and memory expander improvements included in the specification.View the Press ReleaseCXL BlogsFind the latest Consortium news and educational materials on the technology.Read our BlogsUpcoming Industry EventsCXL Consortium representatives regularly support presentations and technology demonstrations during industry eventsView Upcoming Events Previous slide Next
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Compute Express Link (CXL) is an industry-supported Cache-Coherent Interconnect for Processors, Memory Expansion, and Accelerators. It revolutionizes CPU-to-device communication by maintaining memory coherency between CPU memory space and attached devices, enabling resource sharing for higher performance, reduced software complexity, and lower system costs. With CXL, users can focus on their workloads rather than managing redundant memory hardware in accelerators.
As the industry-standard high-speed interface, CXL plays a crucial role in emerging applications like Artificial Intelligence and Machine Learning, where accelerators are increasingly deployed alongside CPUs. The newly released CXL 3. 0 Specification builds upon previous generations, enhancing scalability, fabric management, peer-to-peer communications, and resource sharing across compute domains.
Notable features of the CXL 3. 0 Specification include multi-headed and fabric attached devices, efficient fabric management, composable disaggregated infrastructure, enhanced scalability, improved memory pooling, multi-level switching, and expanded coherency capabilities. It also offers improved software capabilities, doubling the bandwidth to 64GTs with zero added latency over CXL 2.
0. Stay updated with the full details by downloading the CXL 3. 0 white paper.
Experience the power of Compute Express Link, the breakthrough interconnect propelling computational efficiency to new heights
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